1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to various methods of controlling properties and characteristics of a gate insulation layer based upon electrical test data, and a system for performing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor or the thinner the gate insulation layer, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
Memory devices such as erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), or flash erasable programmable read-only memories (FEPROMs) are, as their name indicates, erasable. Such erasable memory cells are used in a variety of different devices, e.g., digital cellular phones, digital cameras, LAN switches, cards for notebook computers, etc. A memory cell operates by storing electric charge (representing an “on” state) to an electrically isolated floating gate, which is incorporated into a transistor. This stored charge affects the behavior of the transistor, thereby providing a way to read the memory element. The switching speed of such a memory cell for converting from an “on” state to an “off” state is limited in part by the speed of charge dissipation from the floating gate (i.e., the erase speed). Because faster erase speeds equate to faster switching speeds, efforts have been made to increase the erase speeds of such memory devices, as well as to improve the erase uniformity among the memory cells.
A flash memory cell typically consists of a source region, a drain region, a tunnel oxide layer, a floating gate, an insulating layer of oxide, a layer of silicon nitride, another layer of oxide, and a control gate positioned above the floating gate in a stacked gate structure. The floating gate, typically comprised of polycrystalline silicon (i.e., “polysilicon”), is electrically isolated from the underlying semiconductor substrate by a thin gate insulation layer, which is typically formed of silicon oxide. Because charge is transferred across the gate insulation layer by quantum-mechanical tunneling, this gate insulation layer is often referred to as a “tunnel oxide” layer. Such tunnel oxide layers are typically approximately 100 Å thick. Properties of the tunnel oxide layer must be strictly controlled to ensure the ability to read and write by tunneling, while avoiding data loss through charge trapping or leakage. The control gate is positioned above the floating gate, and is electrically isolated from the floating gate by a storage dielectric layer, such as an oxide-nitride-oxide (ONO) stack.
Storing charge on the floating gate programs a memory cell. This is achieved via hotelectron injection by applying a high positive voltage (approximately 12V) to the control gate, and a high drain-to-source bias voltage (approximately 45V). An inversion region is created between the source and drain by the control gate voltage, and electrons are accelerated from the source to the drain by the drain bias voltage. Some fraction of these electrons will have sufficient energy to surmount the tunnel oxide barrier height and reach the floating gate. The floating gate is therefore programmed by collecting and storing these electrons to represent an “on” state.
The negative charge captured in the floating gate makes the channel more positive and, thus, less conducting. As a result, the threshold voltage is higher for a charged cell than for an uncharged cell. Consequently, for a given voltage applied to the control gate, the non-volatile memory cell will conduct if the floating gate has no stored charge and will not conduct if the floating gate has stored charge. Therefore, a logical low or high is provided by the non-volatile memory cell based on whether or not the cell conducts at a given threshold voltage.
In order to remove charge from the floating gate, the non-volatile memory cell is irradiated with ultraviolet light. The ultraviolet light provides the stored electrons on the floating gate with enough extra energy to cross the barrier of the tunnel oxide layer. However, this is a relatively time-consuming process. To reduce the time required to complete this process, the temperature of non-volatile memory arrays may be elevated during erasure to add to the energy obtained from the ultraviolet light. The use of elevated temperatures, however, has led to a high incidence of breakage of the relatively thin wafers on which the non-volatile memory arrays are fabricated.
Flash memory devices are a type of EEPROM (Electrically Erasable Programmable Read-Only Memory). The term “flash” refers to the ability of the memory to be erased in blocks. As in other non-volatile memory devices, flash memory devices typically store electrical charges, representing data, in transistors having either a floating gate or a charge trapping dielectric. The stored charges affect the threshold voltage of the transistors. For example, in an n-channel floating gate transistor, an accumulation of electrons in the floating gate electrode increases the threshold voltage of the transistor. The presence or absence of the stored charge can be determined by whether current flows between a source region and a drain region of the transistor when appropriate voltages are applied to the control gate, source and drain.
From the foregoing, it should be understood that the manufacture of a gate insulation layer, and controlling the properties thereof, is a very important aspect of manufacturing semiconductor devices, such as transistors and memory devices. What is desired is methods and systems that assist manufacturers in producing gate insulation layers of the desired qualities and characteristics.
The present invention is directed to various methods and systems that may solve, or at least reduce, some or all of the aforementioned problems.